Senior ASIC Timing Engineer, DFT — Nvidia | cvGO!

Nvidia · US, CA, Santa Clara · Office

### About the Role Senior ASIC Timing Engineer, DFT at Nvidia. Responsible for static timing analysis (STA) and verification of DFT structures (scan, MBIST, boundary scan) for high-performance GPUs and SoCs. ### Responsibilities - Perform STA for DFT chains across all design stages. - Develop and op